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NAND wafers

Date: 18 February 2022 Tags: Miscellaneous


Technology company Western Digital (WD) has announced that it has lost 6.5 exabytes (billion gigabytes) worth of NAND flash storage.



WD and its partner Kioxia said that materials used in their fabrication were found to be contaminated.



  • Kioxia’s facility is used by Western Digital to manufacture some of its SSD storage devices. WD and Kioxia were on the talks for a merger.

  • The contamination may have taken place in Kioxia company’s Yokkaichi and Kitakami plants, located in Japan. Impurities got added during manufacture of 3D flash memory ‘BiCS FLASH’”.



  • Kioxia and WD are two of the top-three largest memory manufacturers in the world. This event is likely to have a significant impact on the global computing hardware market.

  • A similar incident had taken place in 2019 when an unexpected power outage in the Yokkaichi region in Japan destroyed 6 exabytes worth of NAND storage. 

  • The shutdown could be buffered during that time as the NAND industry had an ongoing oversupply problem.

  • The shortage will impact personal device manufacturers, enterprise storage systems or cloud service providers.

  • Even layman consumers are likely to be affected as high cost for cloud-service providers could translate to increased prices for downstream customers.


NAND Wafers

NAND wafers are arrangements of a large number of memory cells. They are made-up of logic gates that receive binary inputs and output a single signal.


2D NAND wafers

In this form, memory cells are arranged in a simple two-dimensional matrix. It has limited capacity as the number of memory cells that can be placed within a chip is fixed.



  • To increase memory size, the memory cells have to be increased or increasing the size of the die. 

  • Since increasing die size requires longer connections between memory cells, latency takes place and affects performance. The maximum size is capped at 128 GB.


3D NAND wafers

In this form, memory cells can be stacked in three-dimensional vertical layers instead of a single horizontal layer.



It increased the number of memory cells that a single chip can have. It reduced the distance between memory cells, leading to faster memory performance. 

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